4 methods to construct a CAD circulate: In-house design to custom-EDA device

An inner pc aided design (CAD) or design providers engineer is chargeable for delivering environment friendly, sturdy and high-quality design circulate options. The design circulate on a day-to-day foundation retains chip designers and verification engineers productive and centered on their jobs, stopping them from debugging CAD instruments and flows and creating advert hoc and undocumented scripts. Over the lifetime of a mission, a high-quality design circulate differentiates an organization from rivals and could be the distinction between getting chips to market first or being the sufferer of surprising course of bottlenecks and delays.

And but, each semiconductor mission group offers with inefficiencies that constrain them from delivering perfect options and limits productiveness. At the moment’s CAD engineers use a patchwork of instruments, flows and scripts consisting of economic digital design automation (EDA) merchandise, industrial or in-house personalized add-ons and in-house mental property (IP), an issue for a lot of mission teams due to :

  1. Instrument circulate gaps in current EDA merchandise
  2. The burden of sustaining in-house or homegrown instruments, flows and scripts
  3. The shortage of time to construct and take a look at high-quality, sturdy inner instruments

That inevitably results in a bunch of issues, as defined within the following sections.

Infinite script design loops

The burden of sustaining in-house or homegrown instruments, flows and scripts is one among cascading interventions. It could begin out with a design engineer writing a Perl or Tcl script to beat a roadblock within the design verification course of.

Because the mission group makes use of it, particular circumstances and features do not work. The script will get one other rework to refine it and will get handed as much as the chip lead for evaluation who notes enhanced automation, then notices that the script doesn’t deal with one thing important.

Extra points come up as extra of the mission group makes use of the script. The script will get handed to the interior CAD group for ongoing help and upkeep. Extra points come up as the interior CAD division begins to make use of it. CAD spends three weeks engaged on the script to handle these points and ongoing upkeep requires someday per week.

It is not lengthy earlier than help and upkeep of 1 inner script prices between $50,000 and $100,000 per 12 months. Ultimately, the script was required for the event course of, however the monetary and mission time value is excessive and unpredictable.

The burden of upkeep contains making certain current inner instruments and flows proceed to work. Different upkeep choirs might be including options to current inner instruments and flows, and shifting to a brand new {hardware} description language (HDL), akin to Verilog to SystemVerilog, or including help for an extra HDL resulting from third-party IP. The estimated value of updating only one in-house Perl or Tcl script to help SystemVerilog could be $175,000 and 6 months of mission time.

Time is the enemy

An organization’s major purpose is to get the silicon gadget to market quick. The CAD division’s job is to help the designers and verification engineers, which implies persevering with to prop up the patchwork of instruments, flows and scripts hybridized from industrial EDA merchandise and in-house IP.

The shortage of time to construct sturdy instruments is an issue. A CAD engineer is aware of what she or he desires a device to do, is aware of tips on how to design, implement and take a look at it, however would not have the time to do it.

Homegrown fixes embody:

  • Turning to open-source parser tasks, although they by no means have the total language protection or help for brand spanking new constructs.
  • Rewriting inner flows and scripts and utilizing extra sturdy software program engineering methodologies, a tough activity to justify the assets to “re-do” work.
  • Switching from Perl or Tcl to Python for higher understandability and performance. This doesn’t resolve HDL complexity—the SystemVerilog language reference handbook (LRM) is 1,300 pages of complicated specs.
  • Jury-rigging current industrial EDA instruments to carry out duties they weren’t meant to do typically finally ends up with unsatisfactory outcomes and a dependency on costly licenses.

On the similar time, the mission group is taking an enormous threat if CAD is unable to persistently ship best-in-class design and verification flows. Lacking market home windows and/or delivering silicon that’s not aggressive could be deadly to a semiconductor firm given the brand new product cycles and excessive prices of IC growth.

Options exist and vary from in-house growth of {custom} instruments to buying a personalized device constructed by an EDA firm, with variations in between.

4 methods to construct best-in-class CAD flows


Creating sturdy, high-performance CAD instruments in-house would yield a license-free, proprietary device that might be the key weapon to reliably get a chip to market first. It might require constructing a parser from scratch to detach from any licensing agreements.

Disadvantages are:

  • It may be extraordinarily time consuming.
  • It requires a deep understanding of HDL languages ​​and the way they’re used.
  • Outcomes is probably not sturdy as a result of the underlying infrastructure is weak and untested.
  • The device could have insufficient testing, resulting in an iterative help mannequin.
  • It could not observe new developments in HDL languages.
  • Deployment time might be lengthy, starting from one 12 months to a number of years.


License a C++ parser library and rent a software program growth group to construct {custom} CAD instruments that bypass present limitations. This answer is an outsourced variation of the earlier one. Commercially obtainable parsers provide advantages, together with full-language protection for VHDL, Verilog, SystemVerilog and UPF.

Inner CAD teams are sometimes extra skilled in scripting fashion languages ​​akin to Perl, Tcl and Python and will not have the depth of growth experience in C++. The C++ library could be tough to make use of with out in depth C++ software program growth experience.


Ask an EDA vendor to {custom} construct options/operate wanted to allow a design circulate. A bonus of this answer can be help and upkeep of the requested functionality whether it is built-in into the mainline of the product. A consulting mission by the EDA vendor would imply the duty for extra ongoing consulting providers to keep up the characteristic/operate.

What’s extra, the corporate can be holden to the EDA vendor’s schedule or the seller could not construct or be capable to construct the customization. The EDA vendor could require upfront cost for non-recoverable engineering (NRE) prices and, if the EDA vendor provides requests to its subsequent launch, a personalized characteristic or operate turns into obtainable to rivals. Moreover, if the EDA vendor builds a personalized device, there shall be ongoing obligations for IP points and licensing necessities.

As well as, relying on the character of the mission and engagement, the EDA vendor could present the requested performance to its different prospects, thereby dropping any aggressive benefit related to the options/operate. Many EDA distributors additionally present utility engineering help for customizing their device integration into their prospects’ flows. As a result of any such experience is usually supplied to different main licensees, it isn’t more likely to impart a aggressive benefit.


License a CAD device growth platform that incorporates built-in HDL parsers, industrial-quality databases and help for traditional file codecs for in-house growth utilizing mainstream scripting environments. A platform answer like that is supposed for design, verification and CAD engineers to rapidly create focused {custom} functions for semiconductor design and verification.

A sturdy, high-performing and easy-to-use CAD device growth platform ought to:

  • Present full parsing of Verilog, SystemVerilog, Verilog-AMS, VHDL, Liberty and UPF.
  • An intuitive API with a language acquainted to a {hardware} engineer akin to Python that abstracts complexity and allows particular management when wanted.
  • Be pre-tested on a big set of benchmarks that show typical use circumstances and the entire HDL language behaviors, together with constructs and use circumstances.
  • A help mannequin that describes utilizing the device and entry to consulting providers to complement growth.
  • Totally operational pattern functions simply modified for a consumer’s particular case.

CAD instruments growth platform

The most important problem that inner teams face is having access to sturdy, easy-to-use and keep and frequently supported HDL parsing environments. A CAD device growth platform offering each ease of use and sturdy capabilities would free the group from the boundaries of economic EDA flows whereas providing capabilities to distinguish its design circulate. Further advantages are value financial savings on EDA device licenses, time financial savings in CAD instruments, circulate and script growth and elevated productiveness for design, verification and CAD engineers.

The CAD device growth platform would require an upfront funding, slightly than making use of free scripting instruments like Perl and Tcl, a disadvantage that must be thought-about. With the transfer from Verilog to SystemVerilog, for instance, easy Perl or Tcl scripts should not possible as a result of further complexities of the language. A CAD device growth platform designed for HDL exploration and modification will allow new and modern instruments and flows not potential utilizing general-purpose text-parsing capabilities.

A CAD device growth platform is an funding that enables totally utilized human capital; worthwhile R&D assets enthusiastic about constructing one of the best ICs, not combating to debug advert hoc Perl scripts.

One other disadvantage is the query of robustness of the parsing functionality for SystemVerilog, VHDL or UPF. To achieve success, the platform have to be based mostly on a broadly used and examined HDL parser library. With out it, every new design or mission will reveal extra limitations of the parser. Solely parsers actively utilized by hundreds of engineers and actively maintained can deal with arbitrary new designs.

Closing gaps in a CAD circulate and getting off the countless cycle of script design and debug, a licensed CAD device growth platform supplies the potential to leverage commercial-grade HDL parsers whereas simplifying their use.

Daniel Hoggar is a senior member of technical workers at Verific Design Automation.

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